Liquid crystal display devices, organic EL displays, and the like are known as display devices for various types of equipment such as notebook computers and mobile phones. Generally, in a display device, pixel regions are provided at intersections between scanning lines and signal lines, and disposed in each pixel region are, for example, display elements such as pixel electrodes, and thin film transistors for driving.
A configuration for detecting the amount of light received has been proposed in which photosensors that employ a photodetection element such as a photodiode are disposed in alignment with the display elements in the pixel region in such a display device (e.g., JP 2002-182839A and WO 2007/145346). Such a configuration enables detecting the brightness of external light and picking up an image of an object that has come close to the reading surface.
In a conventional liquid crystal display device including this type of photosensor, a MOS image sensor is configured by disposing photosensors in alignment with liquid crystal pixel portions arranged at intersections between scanning lines and signal lines. The photosensors configuring the MOS image sensor each include a photodiode, a storage capacitor that stores a charge in accordance with the amount of light received by the photodiode, a MOS transistor, and various types of control lines for controlling the operations of these members. In the photosensors, switching of the MOS transistor and the like is performed using a signal supplied from a control line, thus controlling the resetting of the charge of the storage capacitor and the reading out of charge from the storage capacitor.
FIG. 12 shows the configuration of the photosensor disclosed in JP 2002-182839A. The cathode of a photodiode DL is connected to a storage node N1. Furthermore, a first terminal of a storage capacitor C1 and the gate of a MOS transistor M1 are connected to the storage node N1. The anode of the photodiode DL is connected to a reset control line RST. A second terminal of the storage capacitor C1 is connected to a readout control line RS. A voltage VDD is supplied to the source of the MOS transistor M1 during signal readout, and the drain of the MOS transistor M1 is connected to a signal readout line SL. This photosensor can be disposed with a small occupied area due to the ability to operate with only one MOS transistor M1.
A description will now be given of operations of the photosensor shown in FIG. 12, with reference to FIG. 13. In FIG. 13, (a) shows a waveform of change in the potential of the storage node N1 that accompanies change in signals. In FIG. 13, (b) shows a voltage waveform of the reset signal supplied to the reset control line RST, and (c) shows a voltage waveform of the readout signal applied to the readout control line RS. This photosensor operates by the repetition of a cycle including a reset period, a storage period, and a readout period.
First, at the start of the reset period, as shown in (b) of FIG. 13, the reset signal of the reset control line RST transitions from low level VRSTL to high level VRSTH. At this time, as shown in (c) of FIG. 13, the readout signal of the readout control line RS is in the low level VRSL state. Accordingly, the photodiode DL enters the forward biased state, and a voltage at high level VRSTH is applied to the storage capacitor C1 via the storage node N1. As a result, in the reset period, the storage capacitor C1 is charged and enters a pre-charged state, and as shown in (a) of FIG. 13, the potential of the storage node N1 reaches VRSTH. Here, VRSTH is set so as to be lower than the threshold voltage of the MOS transistor M1. Accordingly, the MOS transistor M1 is in the off state in the reset period and the subsequent storage period.
Thereafter, when the reset signal returns to low level VRSTL as shown in (b) of FIG. 13, the photodiode DL enters the reverse biased state, and the storage period is started. Instantly at this time, the charge of the storage capacitor C1 is partially discharged via the parasitic capacitance of the photodiode DL, and as shown in (a) of FIG. 13, the potential of the storage node N1 drops by a constant voltage (VFD1) to VN10. This phenomenon is called “feedthrough”.
In the storage period, current flows from the storage node N1 to the reset control line RST via the photodiode DL due to charge generated in accordance with the amount of light received by the photodiode DL. Then, as shown in (a) of FIG. 13, the potential of the storage node N1 gradually decreases from VN10, and reaches VN11 at the end of the storage period. This potential VN11 of the storage node N1 is also set so as to not exceed the threshold voltage of the MOS transistor M1.
When the readout period starts, as shown in (c) of FIG. 13, the voltage of the readout signal rises to high level VRSH, and VDD is supplied to the source of the MOS transistor M1. Due to the readout signal reaching high level VRSH as described above, charge implantation occurs via the storage capacitor C1, and as shown in (a) of FIG. 13, the potential of the storage node N1 rises to a readout potential VG1. Since the potential VG1 is set so as to exceed the threshold voltage of the MOS transistor M1, the MOS transistor M1 is turned on, and an output signal that is in accordance with the potential of the storage node N1 is read out via the signal readout line SL.
When the readout period ends, as shown in (c) of FIG. 13, the readout signal returns to low level VRSL, and the source of the MOS transistor M1 is cut off from VDD. Accordingly, the charge in the storage node N1 is discharged via the storage capacitor C1, and the potential of the storage node N1 returns to the value VN11, which is lower than the threshold voltage of the MOS transistor M1.
According to the above operations, in the reset period, the storage node N1 is reset (pre-charged) via the photodiode DL. Then, in the storage period, the potential of the storage node N1 changes in accordance with the charge generated in the photodiode DL. In the readout period, the change in the potential of the storage node N1 is readout by the MOS transistor M1, thus obtaining photodetection output.